The present invention relates generally to capacitance measurements and more specifically to the method of measuring capacitance of micro structures in an integrated circuit.
The capacitance of micro structures of an integrated circuit are in the range of femto-farads These capacitance's are between conductors or interconnects on an integrated circuit as well as the parasitic capacitance between regions of the integrated circuit at their PN junctions and between the regions and the conductors or interconnects. Micro structures or elements may include LSI, DRAM or ROM or other arrays. They may also include individual elements of these arrays, for example, a field effect transistor, word-line, bit-line, access transistor structure, cell plate, memory capacitor ETC.
Historically, there was no way to measure the actual capacitance between micro elements. In order to determine very small capacitance and examine the integrated circuits, the prior art made multiple number models of the integrated circuits. The number of models were between 100-1000 models.
A method for parasitic interconnect capacitor measurements with 0.01 fF or 10 af sensitivity using an efficient test structure on a chip is described in An On-chip, Attofarad Interconnect Charge-Based Capacitive Measurement (CBMC) Technique by James C. Chen et al., 0-7803-3393-4/96 IEEE. The on-chip structure technique were used to measure interconnect geometry capacitance between two crossing metals as well as metal capacitance over a silicon substrate.
The present invention is a method of measuring capacitance of micro structures in an integrated circuit wherein the micro structure includes a first terminal and a second terminal separated by an insulator and at least a third terminal separated from the first terminal by an insulator. The method comprises applying biasing voltage to the second terminal and applying the same potential to the first and third terminals. An electrical characteristic between the first and second terminals are measured to determined the capacitance between the first and second terminals. The integrated circuit may include a plurality of third terminals, each separated from the first terminal by an insulator. The method would further include applying the same potential to the first terminal and all the third terminals so as to measure only the capacitance between the first and second terminals.
The integrated circuit may also include a fourth terminal separated from the first terminal by an insulator. The method may include applying the biasing voltage to the second and fourth terminals and measuring the voltage between the first terminal and the second and fourth terminals. This determines the sum of the capacitance between the first terminal and the second and fourth terminals. Although the first and third or fourth terminals are connected to the same potential, the measurements are taken at the first terminal.
Wherein the micro structure is a field affect transistor, the capacitance between the gate and the source or drain may be measured by applying the biasing voltage to one of the source and drain and applying the same potential to the gate and to the channel area and the other of the source and drain. Then the electrical characteristic is measured between the gate and one of the source and drain to determine the capacitance between the gate and one of the source and drain. Alternatively, the capacitance between the gate and one of the source and drain can be measured by biasing the gate and applying the same potential to the source and to the drain. The biasing voltage may be connected to both the source and drain with the gate and the body connected to the same potential. This would produce the sum of the capacitance between the gate and the source and drain.
The capacitance of the PN junction between the source and drain and the body may also be measured. This would include applying the biasing voltage to the body and applying the same voltage to one of the source or drain and to the gate and the other to the source and drain. The electrical characteristics between the selected one of the source or drain and the body is measured to determine the capacitance of the PN junction therebetween. In an insulated gate field effect transistor, the channel area has applied the biasing voltage and the gate source and drain have the same potential. The voltage between the gate and the channel is measured to determine the capacitance between the gate and the channel through the gate insulator.
Wherein the integrated circuit includes a memory array of cells wherein each cell has a cell plate, transistor connected to a word line and a bit line and a body, the capacitance of the various micro structures may be measured. The capacitance between the neighboring lines may be measured by biasing a bit or word line and applying the same potential to a neighboring bit or word line and to the cell plate and the body. Then an electrical characteristic between the word or bit line and its other neighbor word or bit line is measured to determine the capacitance therebetween. By biasing a pair of neighbor bit or word lines, the sum of the capacitance between the bit or word line and both of its neighbors may be measured. Preferably, the access transistor of the cells and the bit ore word line drives and switches are turned off.
The method also includes providing a pad on the integrated circuit connected to the bit or word line and a separate pad for the cell plate and the body. A shield of electrodes are also provided on the integrated circuit adjacent the pad for being connected to the same potential as the word or bit line.
The same method may be used to determine the capacitance between a conductor and its neighboring conductor separated by insulators. This is between conductors on the same level and on different levels of the integrated circuit.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.